Category: Seminars and Conferences
State: Current
November 8th, 2016

Seminar announcement: Test Optimization for Multi-Core/Multi-Vdd 2D & 3D SoCs

2 p.m. - meeting room L. Ciminiera at the 5th floor of DAUIN

Dynamic voltage and frequency scaling (DVFS) combined with the partitioning of the System-on-Chip (SoC) into multiple voltage islands constitutes a powerful dynamic-power minimization technique. However, the sharing of the test-access mechanisms (TAMs) among different voltage islands, the necessity to test every core at multiple voltage levels and the low shift-frequency limits at the lower voltage levels introduce new test challenges and dramatically increase testing time. In this presentation, we unfold challenges related to scheduling tests for DVS-based SoCs, and we describe recent advances for minimizing the test time in 2-dimensional as well as 3-dimensional multi-Vdd SoCs with multiple voltage islands.

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